1. Field of the Invention
The present invention relates to verification of functional relationships between logic signals, and in particular, to verification of logical exclusivity among a group of logic signals.
2. Description of the Related Art
A common problem faced by logic designers is that of verifying functional relationships among a group of logic signals. For example, the control signals responsible for enabling and disabling a C-MOSFET transmission gate must be opposite in phase, or polarity, from one another so as to properly enable and disable their respective MOSFETs at the correct times. Accordingly, the functional relationship between these signals, i.e. that of opposing phases, must be ensured.
Such logic signal validity verification is particularly important in the case of decoded multiplexors. As is well known, the data select signals for decoded multiplexors are predecoded, with each data input having its own distinct data select line (or its own distinct pair of data select lines for differential data select signals) associated with them. Since only one valid data signal can be passed through the multiplexor at any one time, only one data select signal is allowed to be active at such time, otherwise a data conflict will occur thereby resulting in undefined signal values at the data output. (Decoded, i.e. as opposed to encoded, multiplexors are often used because of their reduced integrated circuit chip area requirements and faster operational speeds due to their ability to share data select signal decoding circuitry among multiple multiplexors.)
Conventionally, numerous techniques have been used for verifying functional relationships among a group of logic signals. One such technique relies upon the development of a solution for a customized logic equation using a Binary Decision Diagram ("BDD") approach. (A discussion of BDDs can be found in R. E. Bryant, "Graph Based Algorithms For Boolean Function Manipulation," IEEE Transactions on Computers, August 1986, pp. 677-91.) However, the size of the BDD required quickly becomes a limiting factor when using this technique.
Accordingly, it would be desirable to have a logic signal validity verification technique with which the validity of functional relationships among a group of logic signals can be more quickly and easily verified.